This invention relates to an integrator circuit for integrating an input signal in the form of a sampled analog current, the integrator comprising input means for receiving the input signal, output means for producing as an output signal the integrated input signal, a current memory cell for producing at its output during a first portion of each sampling period a current related to that applied to its input during a second portion of that or a preceding sampling period, means for coupling the output of the current memory cell to the integrator output means, and feedback means for applying a feedback signal to the input of the current memory cell during the second portion of each sampling period.
An integrator circuit as set forth in the preceding paragraph has been disclosed in a paper by J. B. Hughes, N. C. Bird, and I. C. Macbeth entitled "Switched Currents--A New Technique for Analogue Sampled-Data Signal Processing" which was presented to The Institution of Electrical Engineers on 17th Feb. 1989.
FIG. 1 illustrates an integrator circuit as set forth in the opening paragraph while FIG. 2 shows the clock waveforms used to operate the switches in the circuit of FIG. 1.
The integrator circuit shown in FIG. 1 has an input 1 which is connected to the junction of a current source 2 and the drain electrode of an n-channel field effect transistor T1. The other end of the current source 2 is connected to a positive supply rail 3 while the source electrode of transistor T1 is connected to a negative supply rail 4. The drain electrode of transistor T1 is connected to its gate electrode and to one end of a switch S1. The other end of the switch S1 is connected to the junction of a capacitor C1 and the gate electrode of an n-channel field effect transistor T2. The source electrode of transistor T2 and the other end of the capacitor C1 are connected to the negative supply rail 4. The drain electrode of transistor T2 is connected to the drain electrode of a p-channel field effect transistor T3 whose source electrode is connected to the positive supply rail 3. The drain electrode of transistor T3 is connected to its gate electrode and to one end of a switch S2. The other end of the switch S2 is connected to the junction of the gate electrode of a p-channel field effect transistor T4 and a capacitor C2. The source electrode of transistor T4 and the other end of capacitor C2 are connected to the positive supply rail 3. The gate electrode of transistor T4 is further connected to the gate electrode of a p-channel field effect transistor T6 whose source electrode is connected to the positive supply rail 3. The drain electrode of transistor T4 is connected to the drain electrode of an n-channel field effect transistor T7 whose source electrode is connected to the negative supply rail 4. The drain of transistor T4 is connected via a feedback connection 10 to the drain electrode of transistor T1. A current source 9 is connected between the positive supply rail 3 and the drain electrode of an n-channel field effect transistor T10 whose source electrode is connected to the negative supply rail 4. The drain electrode of transistor T10 is connected to its gate electrode, to the gate electrode of transistor T7, and to the gate electrode of an n-channel field effect transistor T9. The source electrode of transistor T9 is connected to the negative supply rail 4 while its drain electrode is connected to the drain electrode of transistor T6 and to an output terminal 7.
The operation of the circuit shown in FIG. 1 is as follows. Input 1 is fed by a current i which is a sampled current and remains substantially constant during each sampling period and changes in successive sampling periods to follow the continuous analogue signal from which it is derived. A feedback current i.sub.f, which is the difference between the currents produced by transistors T4 and T7, is produced in the feedback path 10 while an output current i.sub.o, which is the difference between the currents produced by transistors T6 and T9, is produced at the output 7. The current sources 2 and 9 each produce a bias current j. The ratios of the currents conducted by transistors T3, T4 and T6 are arranged to be 1:B:A, while the ratios of the currents conducted by transistors T10, T9 and T7 are arranged to be 1:A:B. Switch S1 is arranged to be closed during a portion .phi. of each sampling period while switch S2 is arranged to be closed during a non-overlapping portion .phi. of each sampling period.
During the .phi. part sampling period (n-1), see FIG. 2, the current i(n-1) is applied to input 1 and this current together with the bias current j produced by current source 2 and a feedback current i.sub.f on line 10 is applied to the input of the first memory cell. As a result a current I.sub.2 is produced by transistor T2 which can be derived from the equation ##EQU1##
During the .phi. portion of sampling period n the switch S1 is open but the current I.sub.2 is maintained at its previous value by the charge on capacitor C1. Consequently the current I.sub.2 =i(n-1)+j+i.sub.o (n-1) B/A is fed to the input of the second memory cell and as switch S2 is closed a current I.sub.4 is produced by transistor T4 and a current I.sub.6 is produced by transistor T6. The current I.sub.4 is equal to BI.sub.2 while the current I.sub.6 is equal to AI.sub.2. Consequently the current I.sub.6 during the sampling period n is given by the expression EQU I.sub.6 (n)=A[i(n-1)+j+i.sub.o (n-1)B/A].
The current i.sub.o (n) is given by I.sub.6 (n)-Aj. Consequently ##EQU2## Converting to the z-domain: EQU i.sub.o (z)=A i(z)z.sup.-1 +B i.sub.o (z)z.sup.-1
therefore ##EQU3## The continuous time lossy integrator is described by ##EQU4## Using the forward Euler transform ##EQU5## Thus B=1 corresponds to a=0 and gives lossless integration. The integrator shown in FIG. 1 can be modified to perform according to the backward Euler transform by connecting the input 1 to the drain electrode of transistor T2 instead of to the drain electrode of transistor T1.
This integrator circuit which is disclosed in FIG. 20 of the co-pending UK patent application No. 8816072.6, which corresponds to U.S. Pat. No. 4,958,123 (9/18/90), has certain disadvantages. For proper operation it relies on the feedback current i.sub.f being an exact replica of the current applied to the drain electrode of transistor T1 in the preceding sample period (minus the bias current j). However, the accuracy of this feedback current can be impaired by a number of factors. First, if the gain of the feedback loop becomes greater than unity the system becomes unstable. Conversely, if the gain is less than unity the integrator becomes lossy, that is the inverter becomes a first order low pass filter whose cut off frequency becomes highly sensitive to small changes in the gain if the cut off frequency is much less than the clock frequency. The gain of the feedback loop is in turn directly determined by the matching between transistors T1 and T2 and between transistors T3 and T4. Secondly, the switches S1 and S2 introduce clock feedthrough which distorts the signal and accumulates in the integrator causing d.c. offsets at the output of the integrator. Thirdly, for each of the current memory cells there is a time constant set up due to the 1/gm of the diode connected transistor, the `on-resistance` of the switch, and the gate capacitance (and additional capacitance if provided) of the output transistor. This filters the signal in the non-linear voltage domain and causes signal distortion. Furthermore, a delay determined by this time constant and the frequency of the sampled signal changes the effective value of the unit delay z.sup.-1 which corrupts the filter characteristics.